| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
< data not available > |
| Path | C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt64; C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt64; C:\Xilinx\14.1\ISE_DS\ISE\bin\nt64; C:\Xilinx\14.1\ISE_DS\ISE\lib\nt64; C:\Xilinx\Vivado\2012.1\bin; C:\Xilinx\14.1\ISE_DS\PlanAhead\bin; C:\Xilinx\14.1\ISE_DS\EDK\bin\nt64; C:\Xilinx\14.1\ISE_DS\EDK\lib\nt64; C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt64\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt64\bin; C:\Xilinx\14.1\ISE_DS\common\bin\nt64; C:\Xilinx\14.1\ISE_DS\common\lib\nt64; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\DMIX; C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\; C:\Program Files\OpenAFS\Common; C:\Program Files\OpenAFS\Client\Program; C:\Program Files (x86)\OpenAFS\Common; C:\Program Files (x86)\OpenAFS\Client\Program; C:\Program Files\MATLAB\R2011a\runtime\win64; C:\Program Files\MATLAB\R2011a\bin; C:\Program Files\TortoiseSVN\bin; C:\Users\real\AppData\Local\Smartbar\Application\ |
C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt64; C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt64; C:\Xilinx\14.1\ISE_DS\ISE\bin\nt64; C:\Xilinx\14.1\ISE_DS\ISE\lib\nt64; C:\Xilinx\Vivado\2012.1\bin; C:\Xilinx\14.1\ISE_DS\PlanAhead\bin; C:\Xilinx\14.1\ISE_DS\EDK\bin\nt64; C:\Xilinx\14.1\ISE_DS\EDK\lib\nt64; C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt64\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt64\bin; C:\Xilinx\14.1\ISE_DS\common\bin\nt64; C:\Xilinx\14.1\ISE_DS\common\lib\nt64; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\DMIX; C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\; C:\Program Files\OpenAFS\Common; C:\Program Files\OpenAFS\Client\Program; C:\Program Files (x86)\OpenAFS\Common; C:\Program Files (x86)\OpenAFS\Client\Program; C:\Program Files\MATLAB\R2011a\runtime\win64; C:\Program Files\MATLAB\R2011a\bin; C:\Program Files\TortoiseSVN\bin; C:\Users\real\AppData\Local\Smartbar\Application\ |
C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt64; C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt64; C:\Xilinx\14.1\ISE_DS\ISE\bin\nt64; C:\Xilinx\14.1\ISE_DS\ISE\lib\nt64; C:\Xilinx\Vivado\2012.1\bin; C:\Xilinx\14.1\ISE_DS\PlanAhead\bin; C:\Xilinx\14.1\ISE_DS\EDK\bin\nt64; C:\Xilinx\14.1\ISE_DS\EDK\lib\nt64; C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt64\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt64\bin; C:\Xilinx\14.1\ISE_DS\common\bin\nt64; C:\Xilinx\14.1\ISE_DS\common\lib\nt64; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\DMIX; C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\; C:\Program Files\OpenAFS\Common; C:\Program Files\OpenAFS\Client\Program; C:\Program Files (x86)\OpenAFS\Common; C:\Program Files (x86)\OpenAFS\Client\Program; C:\Program Files\MATLAB\R2011a\runtime\win64; C:\Program Files\MATLAB\R2011a\bin; C:\Program Files\TortoiseSVN\bin; C:\Users\real\AppData\Local\Smartbar\Application\ |
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| XILINX | C:\Xilinx\14.1\ISE_DS\ISE\ | C:\Xilinx\14.1\ISE_DS\ISE\ | C:\Xilinx\14.1\ISE_DS\ISE\ | < data not available > |
| XILINXD_LICENSE_FILE | C:\.Xilinx\Xilinx.lic | C:\.Xilinx\Xilinx.lic | C:\.Xilinx\Xilinx.lic | < data not available > |
| XILINX_DSP | C:\Xilinx\14.1\ISE_DS\ISE | C:\Xilinx\14.1\ISE_DS\ISE | C:\Xilinx\14.1\ISE_DS\ISE | < data not available > |
| XILINX_EDK | C:\Xilinx\14.1\ISE_DS\EDK | C:\Xilinx\14.1\ISE_DS\EDK | C:\Xilinx\14.1\ISE_DS\EDK | < data not available > |
| XILINX_PLANAHEAD | C:\Xilinx\14.1\ISE_DS\PlanAhead | C:\Xilinx\14.1\ISE_DS\PlanAhead | C:\Xilinx\14.1\ISE_DS\PlanAhead | < data not available > |
| XILINX_VIVADO | C:\Xilinx\Vivado\2012.1 | C:\Xilinx\Vivado\2012.1 | C:\Xilinx\Vivado\2012.1 | < data not available > |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | FPGA.prj | ||
| -ofn | FPGA | ||
| -ofmt | NGC | NGC | |
| -p | xc7k325t-2-ffg900 | ||
| -top | FPGA | ||
| -opt_mode | Optimization Goal | Speed | Speed |
| -opt_level | Optimization Effort | 1 | 1 |
| -power | Power Reduction | NO | No |
| -iuc | Use synthesis Constraints File | NO | No |
| -keep_hierarchy | Keep Hierarchy | No | No |
| -netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized |
| -rtlview | Generate RTL Schematic | Yes | No |
| -glob_opt | Global Optimization Goal | AllClockNets | AllClockNets |
| -read_cores | Read Cores | YES | Yes |
| -write_timing_constraints | Write Timing Constraints | NO | No |
| -cross_clock_analysis | Cross Clock Analysis | NO | No |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100 |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100 |
| -dsp_utilization_ratio | DSP Utilization Ratio | 100 | 100 |
| -reduce_control_sets | Auto | Auto | |
| -fsm_extract | YES | Yes | |
| -fsm_encoding | Auto | Auto | |
| -safe_implementation | No | No | |
| -fsm_style | LUT | LUT | |
| -ram_extract | Yes | Yes | |
| -ram_style | Auto | Auto | |
| -rom_extract | Yes | Yes | |
| -shreg_extract | YES | Yes | |
| -rom_style | Auto | Auto | |
| -auto_bram_packing | NO | No | |
| -resource_sharing | YES | Yes | |
| -async_to_sync | NO | No | |
| -use_dsp48 | Auto | Auto | |
| -iobuf | YES | Yes | |
| -max_fanout | 100000 | 100000 | |
| -bufg | 32 | 32 | |
| -register_duplication | YES | Yes | |
| -register_balancing | No | No | |
| -optimize_primitives | NO | No | |
| -use_clock_enable | Auto | Auto | |
| -use_sync_set | Auto | Auto | |
| -use_sync_reset | Auto | Auto | |
| -iob | Auto | Auto | |
| -equivalent_register_removal | YES | Yes | |
| -slice_utilization_ratio_maxmargin | 5 | 0 | |
| Translation Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -intstyle | ise | None | |
| -dd | _ngo | None | |
| -p | xc7k325t-ffg900-2 | None | |
| -uc | D:/KM3NeT_SNV_Repo/KM3NeT/test_designs/LM32_Test_Valencia/Synt/fpga.ucf | None | |
| Map Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ol | Place & Route Effort Level (Overall) | high | high |
| -xt | Extra Cost Tables | 0 | 0 |
| -ir | Use RLOC Constraints | OFF | OFF |
| -t | Starting Placer Cost Table (1-100) Map | 1 | 0 |
| -r | Register Ordering | 4 | 4 |
| -intstyle | ise | None | |
| -lc | LUT Combining | off | off |
| -o | FPGA_map.ncd | None | |
| -w | true | false | |
| -pr | Pack I/O Registers/Latches into IOBs | off | off |
| -p | xc7k325t-ffg900-2 | None | |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Core(TM)2 Quad CPU Q9400 @ 2.66GHz/2660 MHz | Intel(R) Core(TM)2 Quad CPU Q9400 @ 2.66GHz/2660 MHz | Intel(R) Core(TM)2 Quad CPU Q9400 @ 2.66GHz/2660 MHz | < data not available > |
| Host | evalu156 | evalu156 | evalu156 | < data not available > |
| OS Name | Microsoft Windows 7 , 64-bit | Microsoft Windows 7 , 64-bit | Microsoft Windows 7 , 64-bit | < data not available > |
| OS Release | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) | < data not available > |