Core Name: Xilinx LogiCORE Aurora 8B10B
Version: 8.1
Release: ISE 14.1 / Vivado 2012.1
Release Date: April 24, 2012
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This document contains the following sections:
1. Introduction
2. New Features
2.1 ISE
2.2 Vivado
3. Supported Devices
3.1 ISE
3.2 Vivado
4. Resolved Issues
4.1 ISE
4.2 Vivado
5. Known Issues
5.1 ISE
5.2 Vivado
6. Technical Support
7. Other Information
8. Core Release History
9. Legal Disclaimer
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1. INTRODUCTION
For installation instructions for this release, please go to:
www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Aurora 8B10B v8.1
solution. For the latest core updates, see the product page at:
www.xilinx.com/aurora
................................................................................
2. NEW FEATURES
2.1 ISE
- ISE 14.1 software support
- Virtex-7/Kintex-7 GES silicon support
- Scrambler/Descrambler support
2.2 Vivado
- 2012.1 software support
- Virtex-7/Kintex-7 GES silicon support
- Scrambler/Descrambler support
................................................................................
3. SUPPORTED DEVICES
3.1 ISE
The following device families are supported by the core for this release.
Virtex-7
Virtex-7 XT
Virtex-7 Low Voltage (-2L)
Defense Grade Virtex-7Q (XQ)
Defense Grade Virtex-7Q Low Voltage (XQ,-2L)
Kintex-7
Kintex-7 Low Voltage (-2L)
Defense Grade Kintex-7Q (XQ)
Defense Grade Kintex-7Q Low Voltage (XQ,-2L)
Virtex-6 CXT/LXT/SXT/HXT
Virtex-6 Lower Power (-1L) LXT/SXT
Defense Grade Virtex-6Q (XQ) LXT/SXT
Defense Grade Virtex-6Q Lower Power (XQ,-1L) LXT/SXT
Spartan-6 LXT
Automotive Spartan-6 LXT
Defense Grade Spartan-6Q LXT
3.2 Vivado
Virtex-7
Virtex-7 XT
Virtex-7 Low Voltage (-2L)
Defense Grade Virtex-7Q (XQ)
Defense Grade Virtex-7Q Low Voltage (XQ,-2L)
Kintex-7
Kintex-7 Low Voltage (-2L)
Defense Grade Kintex-7Q (XQ)
Defense Grade Kintex-7Q Low Voltage (XQ,-2L)
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- Add support for xc7vx485tl device
CR number 649967
- Provide constraints for xc7k325t-ffg900 on KC724 board
CR number 641086
- Maximum allowed 7-Series GTX reference clock frequency increased from 670MHz to 700MHz in -3 devices
CR number 640170
- 13.3 - Aurora 8b10b v7.1 - GT Reset Requirement is not followed
CR number 633477
- ISE 13.3 - Aurora 8b10b v 7.1 - UG 766 - GSR_DONE_IN signal is not documented
CR number 633472
- aurora_8b10b_7.1: 14.1_1218: Coregen_IP_Deliverables structure mismatch
CR number 639421
4.2 Vivado
- Add support for xc7vx485tl device
CR number 649967
- Provide constraints for xc7k325t-ffg900 on KC724 board
CR number 641086
- Maximum allowed 7-Series GTX reference clock frequency increased from 670MHz to 700MHz in -3 devices
CR number 640170
- 13.3 - Aurora 8b10b v7.1 - GT Reset Requirement is not followed
CR number 633477
- ISE 13.3 - Aurora 8b10b v 7.1 - UG 766 - GSR_DONE_IN signal is not documented
CR number 633472
- aurora_8b10b_7.1: 14.1_1218: Coregen_IP_Deliverables structure mismatch
CR number 639421
For a list of all known issues with the Aurora 8B10B core, please refer to
the AR listing of the core found at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
...............................................................................
5. KNOWN ISSUES
5.1 ISE
There are not known issues for v8.1 of this core at time of release.
5.2 Vivado
There are not known issues for v8.1 of this core at time of release.
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
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6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
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7. OTHER INFORMATION
7.1 Quick start recommendations
---------------------------
After generating an Aurora module, you may want to do one of the
following:
(a) Build an Aurora module to try the flow and see it working in
simulation
(b) Integrate the Aurora module with your own design
(c) Remember to set pin constraints in <component_name>_aurora_example.ucf
file before using the aurora_example design
The User Guide explains the Aurora module in detail to help you connect it
to your design and use it in your system.
7.2 Troubleshooting Guide
---------------------
This section presents some common problems you may encounter with
the Aurora 8B/10B design.
(a) Lanes and Channel do not come up in simulation
- The quickest way to debug these problems is to view the signals from
one of the GT instances that are not working.
- Make sure that the GT reference clock and user clocks are all toggling.
Note that only one of the reference clocks should be toggling,
the rest will be tied low.
- Check to see that TXOUTCLK from GT wrapper is toggling.
If they are not toggling, you may have to wait longer for the PMA to
finish locking. You should typically wait about 6-9 us for lane up
and channel up. Need to wait longer for simplex designs.
- Make sure that TXN and TXP are toggling. If they are not, make sure
you've waited long enough (see the previous bullet) and make sure
you are not driving the TX signal with another signal.
- Check the PLL_NOT_LOCKED signal on your design. If it is held active
high, your Aurora module will not be able to initialize.
- Be sure you do not have the POWER_DOWN signal asserted
- Make sure the TXN and TXP signals from each GT are connected to the
appropriate RXN and RXP signals from the corresponding GT on
the other side of the channel
- If you are simulating Verilog, you will need to instantiate the
"glbl" module and use it to drive the power_up reset at the
beginning of the simulation to simulate the reset that occurs
after configuration. You should hold this reset for a few cycles.
The code below can be used an example:
//Simulate the global reset that occurs after configuration at
//the beginning
//of the simulation.
assign glbl.GSR = gsr_r;
assign glbl.GTS = gts_r;
initial
begin
gts_r = 1'b0;
gsr_r = 1'b1;
#(16*CLOCKPERIOD_1);
gsr_r = 1'b0;
end
- If you are using a multilane channel, make sure all the GT on
each side of the channel are connected in the correct order
(b) Channel comes up in simulation but S_AXI_TX_TVALID is never asserted
(never goes high)
- If your module includes flow control but you are not using it, make
sure the request signals are not currently driven low.
S_AXI_NFC_REQ and S_AXI_UFC_TX_REQ are active high: if they are high,
S_AXI_TX_TVALID will stay low because the channel will be allocated
for flow control
- Make sure WARN_CC and DO_CC are not being driven high continuously.
Whenever DO_CC is high on a positive clock edge, the channel is used
to send clock correction characters, so S_AXI_TX_TVALID is deasserted
- If you have NFC enabled, make sure the design on the other side of
the channel did not send an NFC XOFF message. This will cut off
the channel for normal data until the other side sends
an NFC XON message to turn the flow on again. See UG766.pdf for more
details
(c) Bytes and words are being lost as they travel through the Aurora
channel
- If you are using the AXI4-Stream interface, make sure you are writing
data correctly. The most common mistake is to assume words are written
without looking at TVALID. Also remember that the TKEEP signal
must be used to indicate which bytes are valid when TLAST is asserted.
TKEEP will be ignored when TLAST is not asserted (active-high).
- Make sure you are reading correctly from the RX interface. Data and
framing signals are only valid when TVALID is asserted.
(d) Problems while compiling the design
- Make sure you include all the files from the src directory when
compiling
- If you are using VHDL, make sure to include the aurora_pkg.vhd file
in your synthesis
7.3 Links to useful resources
-------------------------
You may find the following resources useful:
7 series FPGAs GTX Transceivers User Guide: UG476.pdf
www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf
Virtex-6 GTX Transceiver User Guide: UG366.pdf
www.xilinx.com/support/documentation/user_guides/ug366.pdf
Spartan-6 GTP Transceiver User Guide: UG386.pdf
www.xilinx.com/support/documentation/user_guides/ug386.pdf
Aurora 8B/10B Protocol Specification: SP002.pdf
www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b_protocol_spec_sp002.pdf
Xilinx on Board:
www.xilinx.com/products/boards-and-kits/boardsearch.htm
(Search for Development boards)
Xilinx Support:
www.support.xilinx.com
8. CORE RELEASE HISTORY
Date By Version Description
================================================================================
04/24/2012 Xilinx, Inc. 8.1 ISE 14.1 and Vivado 2012.1 support
10/19/2011 Xilinx, Inc. 7.1 ISE 13.3 support
Virtex-7/Kintex-7 family support
Synopsys Synplify Pro support
03/01/2011 Xilinx, Inc. 6.2 ISE 13.1 support
PlanAhead support
ISIM Support
projNav flow support
09/21/2010 Xilinx, Inc. 6.1 AXI4-Stream support
ISE 12.3 support
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9. LEGAL DISCLAIMER
(c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
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of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
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